The present invention generally relates to differential comparators, and more specifically to a method and circuit arrangement for adding programmable hysteresis to differential comparators.
Differential comparators are non-linear circuits for sensing either the polarity or magnitude of an input signal. The amplifier output is one of two states, usually for representing the binary states 1 and 0. When the input signal is in excess of a predetermined threshold value (frequently 0), the amplifier output is in one state and when the input signal is less than the predetermined value, the output remains in the other state.
Hysteresis is defined as the difference in the switching point of a circuit for a rising transition and falling transition of the input signal. While generally viewed as a detriment, hysteresis can be employed advantageously in a differential comparator circuit associated with a system having an unknown noise component in which the noise can vary over a wide range in real time. In the case where the input signal has a noise component whose peak to peak value is greater than the hysteresis of the circuit, the circuit will change states back and forth (oscillate) in response to the noise as the input signal approaches the switching threshold of the circuit. Prior art circuits have their hysteresis preset for anticipated noise levels. To increase the hysteresis to be less sensitive to noise reduces the minimum detectable input level and reduces the signal to noise ratio. By providing the differential comparator circuit with a programmable hysteresis, real time noise can be compensated for by appropriately changing the hysteresis level of the comparator circuit. Further, such an approach can be employed to compensate for inter-connected systems having known, but differing noise levels in each system.
Accordingly, it is an object of the present invention to provide a method and circuit arrangement for providing a differential comparator with a programmable hysteresis.
It is a further object of the present invention to provide a method and circuit arrangement for providing a differential comparator with a digitally programmable hysteresis.
It is yet another object of the present invention to provide a method and circuit arrangement wherein the offset voltage in the input stage of a differential comparator is controlled by the output state of the comparator to provide positive feedback and generate hysteresis.
In accordance with the teachings of the present invention, there is provided a method of providing programmable hysteresis to a differential comparator having an input stage with inputs and having an output stage with at least two distinct output states. The method comprises the steps of determining the output state of the output stage and causing a desired offset voltage in the input stage in dependence on the output state of the output stage to provide positive feedback and generate hysteresis.
In accordance with the teachings of the present invention there is also provided a circuit arrangement for providing programmable hysteresis to a differential comparator having an input stage with inputs and having an output stage having at least two distinct output states comprising an output state determining circuit for determining the output state of the output stage and an input offset voltage circuit for causing a desired offset voltage in the input stage in dependence on the output state of the output stage to provide positive feedback and generate hysteresis.
In accordance with certain preferred embodiments of the present invention, the circuit arrangement for providing programmable hysteresis comprises an input offset voltage circuit including a voltage follower for each input of the input stage and an output state determining circuit including a current steering network at the output of the differential comparator. DC bias current sources provide a DC bias current in the current steering network for each input of the input stage. Also included in the current steering network is an offset current source for providing an offset current which is proportional to the level of the desired hysteresis. Current mirrors are provided for each DC bias current so that a mirrored current flows through a corresponding voltage follower of each of the inputs. A transistor circuit is also included for selectively varying one of the DC bias currents by the offset current in dependence on the output state of the output stage. Thus, the voltage of the corresponding voltage follower is varied to effect a desired input stage to produce the hysteresis and provide positive feedback.
According to advantageous features certain preferred embodiments of the present invention, an offset voltage, between the input stage voltage followers, is generated by creating a difference between the voltage follower currents. These currents are controlled by the output state of the comparator to provide positive feedback and generate hysteresis. Further, the bodies of the voltage followers can be tied to their respective sources to eliminate variations in voltage due to body effects.
The control of the voltage follower currents is facilitated by the current steering network at the output of the differential comparator which sets up a DC bias current for each input of the input stage as well as a DC offset current having a magnitude which is proportional to the level of desired hysteresis. The amount of hysteresis is further controlled by the ratio of the magnitude of the DC bias current to the magnitude of the DC offset current.
According to certain further preferred embodiments of the present invention, the magnitude of the offset current can be controlled by a digital-to-analog converter (DAC) to provide digitally programmable hysteresis. Further, a DC bias current and offset current can be generated in a manner so that they have the same temperature and process dependence thereby providing a stable and reliable circuit arrangement.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.